Design Verification Engineering Manager

Intel

Austin, Texas, US
Base: $256,050.00-361,480.00 usd; bonus/equity: st...
Hybrid
Systemverilog uvm development
Coverage-driven verification
Constrained-random testing
Lead and manage a team of design verification engineers, cultivating a culture of collaboration, accountability, and innovation

Job Summary

  • Lead and manage a team of design verification engineers, cultivating a culture of collaboration, accountability, and innovation.
  • Define Project Specific Verification Strategy: Defines and implement scalable and reusable verification plans, test benches, and the verification environments for blocks, subsystems, and SoCs.
  • We offer a total compensation package that ranks among the best in the industry.

Matching Summary

Lead and manage a team of design verification engineers, cultivating a culture of collaboration, accountability, and innovation.

Salary

Base: $256,050.00-361,480.00 USD; Bonus/Equity: stock bonuses; Benefits: health, retirement, and vacation

Skills & Requirements

Must-have

  • SystemVerilog UVM development
  • coverage-driven verification
  • constrained-random testing
  • industry-standard protocols
  • EDA tools
  • debugging skills

Nice-to-have

  • nimble, adaptable, lean and efficient
  • customer impacting technology development
  • collaborative and innovative environment
  • analytical ability and problem-solving skills

Key Requirements

  • Bachelor's degree in STEM
  • 6+ years of experience in ASIC/FPGA design verification
  • Strong understanding of OOP principles
  • Developing UVM and/or Formal based verification architectures
  • Experience with industry standard protocols (AMBA AXI/AXI-S/CHI and communication protocols)
  • Hands-on experience with simulators (Synopsys VCS, Cadence Xcelium, or equivalent)
  • Experience with scripting languages

Work Rights

Not specified

Tailored Resume

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