Sr. Asic Engineer (uvm | System Verilog | Scripting) - 8+ Yrs , Blr

Cisco

Bangalore, India
Proficient in uvm/system verilog
Experience building test benches
7+ years asic design verification
You will engage in dynamic collaboration with verification engineers, designers, and multi-functional teams

Job Summary

  • You will engage in dynamic collaboration with verification engineers, designers, and multi-functional teams.
  • You will contribute to developing Cisco’s progressive data center by crafting industry-leading sophisticated chips.
  • At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era.

Matching Summary

You will engage in dynamic collaboration with verification engineers, designers, and multi-functional teams.

Skills & Requirements

Must-have

  • Proficient in UVM/System Verilog
  • Experience building test benches
  • 7+ years ASIC design verification

Nice-to-have

  • Scripting experience with Perl/Python
  • Experience with data path verification
  • Knowledge of formal verification

Key Requirements

  • Bachelor’s Degree in EE or related field
  • Proficient in verifying sophisticated blocks
  • Experience with Veloce/Palladium/Zebu/HAPS

Work Rights

Not specified

Tailored Resume

Cover Letter