Lead Design Verification Engineer

NXP Semiconductors

Pune, India
Uvm-based verification environments
System verilog
Constrained random verification
Architect, enhance, and maintain advanced UVM-based and C-based verification environments for cutting-edge in-vehicle networking devices

Job Summary

  • Architect, enhance, and maintain advanced UVM-based and C-based verification environments for cutting-edge in-vehicle networking devices.
  • Define robust verification strategies, craft comprehensive test plans, and drive metric-driven verification to full closure.
  • Collaborate closely with world-class teams across Design, Architecture, Validation, and Firmware, ensuring seamless integration and adherence to rigorous automotive design and quality processes.

Matching Summary

Architect, enhance, and maintain advanced UVM-based and C-based verification environments for cutting-edge in-vehicle networking devices.

Skills & Requirements

Must-have

  • UVM-based verification environments
  • System Verilog
  • constrained random verification
  • functional coverage
  • low power verification
  • UPF/CPF Flow
  • SVA Assertion

Nice-to-have

  • collaboration with cross-functional teams
  • driving metric-driven verification
  • automotive design and quality processes

Key Requirements

  • 8+ Years of ASIC/SoC verification experience
  • B.S./M.S. Electrical/Computer Engineering degree
  • Experience with UVM and/or System Verilog
  • Experience with C/C++, Perl, Python scripting
  • Experience with GIT, Jira, Confluence

Work Rights

Not specified

Tailored Resume

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