Dvt Engineer

Celerocommunicationsinc

Irvine, California, United States
Base: $150,000 - $250,000 annually; bonus/equity: ...
On-site
High-speed serdes validation
112g/224g interface characterization
Pam4 signaling expertise
Celerocommunicationsinc is seeking a Senior DVT Engineer specializing in High-Speed SerDes and Line-Side Electrical Characterization for their Optical DSP division in Irvine, California, or Córdoba, Argentina. The role involves leading validation efforts for high-speed interfaces, ensuring electrical integrity in advanced optical transmission systems, and requires expertise in signal processing and electrical characterization

Job Summary

  • This role leads the validation of industry-leading 112G/224G interfaces to ensure foundational stability for multi-terabit coherent transmission.
  • The successful candidate will define test strategies, execute complex silicon characterization, and debug the interface between high-speed electrical signals and the DSP's digital core.
  • Candidates must possess expert-level skills in operating 110GHz+ oscilloscopes and developing Python-based automation for large-scale data analytics.

Matching Summary

Match Score: 85

Celerocommunicationsinc is seeking a Senior DVT Engineer specializing in High-Speed SerDes and Line-Side Electrical Characterization for their Optical DSP division in Irvine, California, or Córdoba, Argentina. The role involves leading validation efforts for high-speed interfaces, ensuring electrical integrity in advanced optical transmission systems, and requires expertise in signal processing and electrical characterization.

Salary

Base: $150,000 - $250,000 Annually; Bonus/Equity: Not specified; Benefits: Not specified

Skills & Requirements

Must-have

  • High-Speed SerDes validation
  • 112G/224G interface characterization
  • PAM4 signaling expertise
  • ADC/DAC performance validation
  • Python automation frameworks
  • OIF-CEI and IEEE 802.3 compliance

Nice-to-have

  • Higher-order PAM modulation experience
  • PhD in High-Speed I/O design
  • Experimental signaling schemes knowledge
  • Multi-terabit coherent transmission background

Key Requirements

  • 5+ years in high-speed hardware validation
  • Bachelor's or Master's in Electrical Engineering
  • Experience with Coherent Optical or networking ASICs

Work Rights

Not specified

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