Base: $127,400 - $180,400 usd; bonus/equity: not s...
On-site
Analog circuit design
Mixed-signal circuit design
High-speed clock distribution
Design various mixed-signal circuit designs on Altera FPGAs such as voltage regulators, bandgaps and bias circuits, Analog to digital converter (ADC), Delay locked loops (DLLs), high speed clock distribution and other clocking circuits, IO circuits such as high voltage IO, RCOMP/SCOMP, memory circuits etc
Job Summary
Design various mixed-signal circuit designs on Altera FPGAs such as voltage regulators, bandgaps and bias circuits, Analog to digital converter (ADC), Delay locked loops (DLLs), high speed clock distribution and other clocking circuits, IO circuits such as high voltage IO, RCOMP/SCOMP, memory circuits etc.
Own specifications and design verification plans covering functionality, performance and reliability meeting high volume productization requirement.
Perform post silicon data analysis and debug and make necessary design enhancement to meet design specification.
Matching Summary
Design various mixed-signal circuit designs on Altera FPGAs such as voltage regulators, bandgaps and bias circuits, Analog to digital converter (ADC), Delay locked loops (DLLs), high speed clock distribution and other clocking circuits, IO circuits such as high voltage IO, RCOMP/SCOMP, memory circuits etc.
Salary
Base: $127,400 - $180,400 USD; Bonus/Equity: Not specified; Benefits: Not specified
Skills & Requirements
Must-have
Analog circuit design
Mixed-signal circuit design
High-speed clock distribution
IO circuits
Advanced process nodes
Design for reliability
AI tool-based design transition
Nice-to-have
Cross-functional team collaboration
Cross-geo team collaboration
Custom analog IP ownership
Key Requirements
BSEE/MSEE/PhD in Electrical Engineering or equivalent
4+ years of experience in analog/mixed signal, high speed, or high voltage IO designs
Direct design experience with analog and mixed signal circuits
Proficient in circuit design tools like Virtuoso, Spice, StarRC, Totem
Understanding of Verilog, static timing analysis, UPF