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Google is seeking a Senior Design Engineer for its AI and Infrastructure team, focusing on delivering advanced capabilities in cloud networking. The role involves defining design specifications and performing RTL development, while collaborating with multi-disciplinary teams.
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Job Summary
The role involves defining block-level design documents including interface protocols and transaction flows for Google Cloud Networking.
Candidates will perform RTL development using Verilog or SystemVerilog and participate in synthesis, timing, and power analysis.
This position requires working with multi-disciplined teams to support the development of cutting-edge AI models and global services.
Matching Summary
Match Score: 75
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Google is seeking a Senior Design Engineer for its AI and Infrastructure team, focusing on delivering advanced capabilities in cloud networking. The role involves defining design specifications and performing RTL development, while collaborating with multi-disciplinary teams.
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Skills & Requirements
Must-have
RTL development in Verilog or SystemVerilog
Block level design documentation
Synthesis and timing/power analysis
FPGA and silicon bring-up experience
Test plan and coverage analysis
Nice-to-have
Multi-site team collaboration
Experience with TPU or Vertex AI platforms
Hyperscale computing background
Key Requirements
Proficiency in VHSIC Hardware Description Language (VHDL)